SDRAM 控制器 Verilog实现

				/**************************************************************************
				*
				*    File Name:  MT48LC2M32B2.V  
				*      Version:  2.1
				*         Date:  June 6th, 2002
				*        Model:  BUS Functional
				*    Simulator:  Model Technology
				*
				* Dependencies:  None
				*
				*        Email:  modelsupport@micron.com
				*      Company:  Micron Technology, Inc.
				*        Model:  MT48LC2M32B2 (512K x 32 x 4 Banks)
				*
				*  Description:  Micron 64Mb SDRAM Verilog model
				*
				*   Limitation:  - Doesn't check for 4096 cycle refresh
				*
				*         Note:  - Set simulator resolution to "ps" accuracy
				*                - Set Debug = 0 to disable $display messages
				*
				*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
				*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
				*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
				*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
				*
				*                Copyright