verilog 写的 memory controller
源代码在线查看： mt48lc2m32b2.v
/**************************************************************************************** * * File Name: MT48LC2M32B2.V * Version: 0.0g * Date: January 12th, 2000 * Model: BUS Functional * Simulator: Model Technology (PC version 5.3 PE) * * Dependencies: None * * Author: Son P. Huynh * Email: sphuynh@micron.com * Phone: (208) 368-3825 * Company: Micron Technology, Inc. * Model: MT48LC2M32B2 (2Meg x 32 x 4 Banks) * * Description: Micron 64Mb SDRAM Verilog model * * Limitation: - Doesn't check for 4096 cycle refresh * * Note: - Set simulator resolution to "ps" accuracy * - Set Debug = 0 to disable $display messages * * Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY * WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR * A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. * * Copyright
