Assembler report for sram
Tue Apr 14 08:32:07 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: F:/毕业设计/毕业设计软件/FPGA/ram/sram.sof
6. Assembler Device Options: F:/毕业设计/毕业设计软件/FPGA/ram/sram.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Apr 14 08:32:07 2009 ;
; Revision Name ; sram ;
; Top-level Entity Name ; sram ;
; Family ; Cyclone II ;
; Device ; EP2C8T144C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; JTAG user code for target device ; Ffffffff ; Ffffffff ;
; Auto user code ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; JTAG user code for configuration device ; Ffffffff ; Ffffffff ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+--------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------+
; File Name ;
+--------------------------------------------+
; F:/毕业设计/毕业设计软件/FPGA/ram/sram.sof ;
; F:/毕业设计/毕业设计软件/FPGA/ram/sram.pof ;
+--------------------------------------------+
+----------------------------------------------------------------------+
; Assembler Device Options: F:/毕业设计/毕业设计软件/FPGA/ram/sram.sof ;
+----------------+-----------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------+
; Device ; EP2C8T144C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x000F33AC ;
+----------------+-----------------------------------------------------+
+----------------------------------------------------------------------+
; Assembler Device Options: F:/毕业设计/毕业设计软件/FPGA/ram/sram.pof ;
+--------------------+-------------------------------------------------+
; Option ; Setting ;
+--------------------+-------------------------------------------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x06EB1F19 ;
; Compression Ratio ; 3 ;
+--------------------+-------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Tue Apr 14 08:32:02 2009
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off sram -c sram
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Allocated 143 megabytes of memory during processing
Info: Processing ended: Tue Apr 14 08:32:08 2009
Info: Elapsed time: 00:00:06
