LCD显示

				module test(SW,LCD_XX);
				
				input  [4:0]SW;
				output [2:0]LCD_XX;
				
				reg [2:0]LCD_XX;
				
				always @(SW)
				
				 begin
				    case(SW)
				      5'b00000:LCD_XX=5'b00001;
				      5'b00010:LCD_XX=5'b00010;
				      5'b00100:LCD_XX=5'b00100;
				      5'b01000:LCD_XX=5'b01000;
				      5'b10000:LCD_XX=5'b10000;
				      endcase
				      
				   end
				   
				 endmodule