vhdl硬件设计实现一个数字上变频器

				`timescale 10ns/1ns				module test;				reg clk;				reg reset;				reg ena;				reg [15:0] datain;								wire [15:0] I_out;				wire [15:0] Q_out;				wire [1:0] cout;				initial				begin					clk=0;					reset=1'b0;					ena=1'b1;					datain=16'b0;					#3 datain=16'b1001_0101_0011_1001;					#10000 $stop; 				end				always #1 clk=!clk;				always @ (negedge clk)				begin					datain				end				ddc ddc(.clk(clk),.ddc_ena(ena),.reset(reset),.I_out(I_out),.Q_out(Q_out),.cout(cout));				endmodule