Release 14.2 Map P.28xd (nt) Xilinx Map Application Log File for Design 'system' Design Information ------------------ Command Line : map -o system_map.ncd -w -pr b -ol high -timing -detail
system.ngd system.pcf Target Device : xc7z020 Target Package : clg484 Target Speed : -1 Mapper Version : zynq -- $Revision: 1.55 $ Mapped Date : Mon Oct 08 09:12:13 2012 WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined
IOSTANDARD. WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained
(LOC) to a specific location. WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined
IOSTANDARD. WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained
(LOC) to a specific location. WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined
IOSTANDARD. WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained
(LOC) to a specific location. Mapping design into LUTs... Writing file system_map.ngm... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 30 secs Total CPU time at the beginning of Placer: 24 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:13d1554b) REAL time: 34 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:13d1554b) REAL time: 34 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:13d1554b) REAL time: 34 secs Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:e6800c5b) REAL time: 38 secs Phase 5.30 Global Clock Region Assignment Phase 5.30 Global Clock Region Assignment (Checksum:e6800c5b) REAL time: 38 secs Phase 6.3 Local Placement Optimization Phase 6.3 Local Placement Optimization (Checksum:e6800c5b) REAL time: 38 secs Phase 7.5 Local Placement Optimization Phase 7.5 Local Placement Optimization (Checksum:e6800c5b) REAL time: 38 secs Phase 8.8 Global Placement ................... .................................................................... ............................................................................ Phase 8.8 Global Placement (Checksum:67eda93b) REAL time: 39 secs Phase 9.5 Local Placement Optimization Phase 9.5 Local Placement Optimization (Checksum:67eda93b) REAL time: 39 secs Phase 10.18 Placement Optimization Phase 10.18 Placement Optimization (Checksum:7c256f96) REAL time: 40 secs Phase 11.5 Local Placement Optimization Phase 11.5 Local Placement Optimization (Checksum:7c256f96) REAL time: 40 secs Phase 12.34 Placement Validation Phase 12.34 Placement Validation (Checksum:7c256f96) REAL time: 40 secs Total REAL time to Placer completion: 40 secs Total CPU time to Placer completion: 32 secs Running post-placement packing... Writing output files... Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 6 Slice Logic Utilization: Number of Slice Registers: 129 out of 106,400 1% Number used as Flip Flops: 129 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 181 out of 53,200 1% Number used as logic: 169 out of 53,200 1% Number using O6 output only: 146 Number using O5 output only: 0 Number using O5 and O6: 23 Number used as ROM: 0 Number used as Memory: 8 out of 17,400 1% Number used as Dual Port RAM: 0 Number used as Single Port RAM: 0 Number used as Shift Register: 8 Number using O6 output only: 8 Number using O5 output only: 0 Number using O5 and O6: 0 Number used exclusively as route-thrus: 4 Number with same-slice register load: 4 Number with same-slice carry load: 0 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 74 out of 13,300 1% Number of LUT Flip Flop pairs used: 199 Number with an unused Flip Flop: 78 out of 199 39% Number with an unused LUT: 18 out of 199 9% Number of fully used LUT-FF pairs: 103 out of 199 51% Number of unique control sets: 14 Number of slice register sites lost to control set restrictions: 47 out of 106,400 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 8 out of 200 4% Number of LOCed IOBs: 8 out of 8 100% Number of bonded IOPAD: 130 out of 130 100% IOB Flip Flops: 8 Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 0 out of 140 0% Number of RAMB18E1/FIFO18E1s: 0 out of 280 0% Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs: 1 Number used as BUFGCTRLs: 0 Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 200 0% Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 200 0% Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 Number of OLOGICE2/OLOGICE3/OSERDESE2s: 8 out of 200 4% Number used as OLOGICE2s: 8 Number used as OLOGICE3s: 0 Number used as OSERDESE2s: 0 Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 16 0% Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 16 0% Number of BSCANs: 0 out of 4 0% Number of BUFHCEs: 0 out of 72 0% Number of BUFRs: 0 out of 16 0% Number of CAPTUREs: 0 out of 1 0% Number of DNA_PORTs: 0 out of 1 0% Number of DSP48E1s: 0 out of 220 0% Number of EFUSE_USRs: 0 out of 1 0% Number of FRAME_ECCs: 0 out of 1 0% Number of ICAPs: 0 out of 2 0% Number of IDELAYCTRLs: 0 out of 4 0% Number of IN_FIFOs: 0 out of 16 0% Number of MMCME2_ADVs: 0 out of 4 0% Number of OUT_FIFOs: 0 out of 16 0% Number of PHASER_REFs: 0 out of 4 0% Number of PHY_CONTROLs: 0 out of 4 0% Number of PLLE2_ADVs: 0 out of 4 0% Number of PS7s: 1 out of 1 100% Number of STARTUPs: 0 out of 1 0% Number of XADCs: 0 out of 1 0% Average Fanout of Non-Clock Nets: 2.02 Peak Memory Usage: 518 MB Total REAL time to MAP completion: 42 secs Total CPU time to MAP completion: 33 secs Mapping completed. See MAP report file "system_map.mrp" for details.
