一些Verilog学习程序B

				Analysis & Synthesis Status : Successful - Sun Jan 11 21:12:54 2009
				Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
				Revision Name : div
				Top-level Entity Name : div
				Family : MAX II
				Total logic elements : 21
				Total pins : 22
				Total virtual pins : 0
				UFM blocks : 0