module bin27seg(clk,reset_n,write_n,writedata,seg_data,seg_com);
input clk;
input reset_n;
//input chipselect;
input write_n;
input [7:0]writedata;
output [7:0]seg_data;
output [7:0]seg_com;
reg [7:0]outdata;
reg [7:0]datain[7:0];
reg [7:0]seg_com;
reg [7:0]seg_data;
reg [7:0]bcd_led;
reg [36:0]count;
reg [31:0] writedata_r;
always @(negedge reset_n or negedge write_n)
begin
if(!reset_n)
begin
datain[0] datain[1] datain[2] datain[3] datain[4] datain[5] datain[6] datain[7] end
else if(!write_n)
begin
writedata_r = writedata*12'd2500/9'd256;
/*
datain[0] datain[1] datain[2] datain[3] datain[0] datain[1] datain[2] datain[3] end
end
always @(posedge clk)
begin
count=count+1;
end
always @(count[14:12])
begin
case(count[14:12])
3'b000:
begin
bcd_led = datain[0];
seg_com = 8'b1111_1110;
end
3'b001:
begin
bcd_led=datain[1];
seg_com=8'b1111_1101;
end
3'b010:
begin
bcd_led=datain[2];
seg_com=8'b1111_1011;
end
3'b011:
begin
bcd_led=datain[3];
seg_com=8'b1111_0111;
end
3'b100:
begin
bcd_led=datain[4];
seg_com=8'b1110_1111;
end
3'b101:
begin
bcd_led=datain[5];
seg_com=8'b1101_1111;
end
3'b110:
begin
bcd_led=datain[6];
seg_com=8'b1011_1111;
end
3'b111:
begin
bcd_led=datain[7];
seg_com=8'b0111_1111;
end
endcase
end
always @(seg_com or bcd_led)
begin
case(bcd_led[3:0])
4'h0:seg_data=8'hc0;
4'h1:seg_data=8'hf9;
4'h2:seg_data=8'ha4;
4'h3:seg_data=8'hb0;
4'h4:seg_data=8'h99;
4'h5:seg_data=8'h92;
4'h6:seg_data=8'h82;
4'h7:seg_data=8'hf8;
4'h8:seg_data=8'h80;
4'h9:seg_data=8'h90;
4'ha:seg_data=8'h88;
4'hb:seg_data=8'h83;
4'hc:seg_data=8'hc6;
4'hd:seg_data=8'ha1;
4'he:seg_data=8'h86;
4'hf:seg_data=8'h8e;
endcase
end
endmodule
