使用verilog和VHDL两种硬件描述语言实现了一个ATA硬盘控制器

				-----------------------------				Revision: 1.0				Date: februar 18th, 2002				Author: Richard Herveille				- initial Verilog release				-----------------------------								-----------------------------				Revision: 1.1				Date: May 19th, 2002.				Author: Richard Herveille				- Fixed a potential bug that forced the core into an unknown state				  when an asynchronous reset was given without a running clock				-----------------------------