《设计与验证Verilog HDL》光盘内容

				@P:  Worst Slack : -0.532
				@P:  asyn_rst|clk - Estimated Frequency : 281.9 MHz
				@P:  asyn_rst|clk - Requested Frequency : 331.7 MHz
				@P:  asyn_rst|clk - Estimated Period : 3.547
				@P:  asyn_rst|clk - Requested Period : 3.015
				@P:  asyn_rst|clk - Slack : -0.532