用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

				Version 5.0 Build 148 04/26/2005 SJ Full Version
				29
				1521
				OFF
				OFF
				OFF
				OFF
				OFF
				FV_OFF
				VRSM_ON
				VHSM_ON
				0
				# entity
				div
				# logic_option {
				AUTO_RAM_RECOGNITION
				ON
				}
				# case_sensitive
				# source_file
				div.v
				1126436908
				7
				# storage
				db|div.(0).cnf
				db|div.(0).cnf
				# internal_option {
				ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
				ON
				AUTO_RESOURCE_SHARING
				OFF
				}
				# hierarchies {
				|
				}
				# end
				# complete