256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual

				ncvlog: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.				TOOL:	ncvlog	05.10-p004: Started on Feb 03, 2005 at 16:49:11				ncvlog				    -work worklib				    -cdslib cds.lib				    -hdlvar hdl.var				    -messages				    -logfile ncvlog.log				    -linedebug				    -status				    ../stim/NAND_TEST.v								file: ../stim/NAND_TEST.v					module worklib.NAND_DRV						errors: 0, warnings: 0					module worklib.test_bench						errors: 0, warnings: 0				ncvlog: Memory Usage - 4.6M program + 2.9M data = 7.4M total				ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.3s, 13.4% cpu)				TOOL:	ncvlog	05.10-p004: Exiting on Feb 03, 2005 at 16:49:11  (total: 00:00:00)