Allegro原理图和PCB
源代码在线查看： top.msg
@TM:1158617706
@N: :"":0:0:0:-1|Gated clock conversion disabled
@N: BN191 :"":0:0:0:-1|Writing property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.tap.
@N: BN225 :"":0:0:0:-1|Writing default property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.map.
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\binary_counter.vhd":6:7:6:20|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":5:7:5:14|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\clockdiv.vhd":20:8:20:9|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\count8.vhd":6:7:6:12|M
@W: CG296 :"c:\actelprj\pa3_demoboard_72\hdl\count8.vhd":21:2:21:8|M
@W: CG290 :"c:\actelprj\pa3_demoboard_72\hdl\count8.vhd":26:11:26:15|M
@W: CG290 :"c:\actelprj\pa3_demoboard_72\hdl\count8.vhd":27:23:27:26|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\data_block.vhd":8:7:8:16|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":9:7:9:9|M
@N: CD231 :"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":23:16:23:17|M
@W: CD604 :"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":101:12:101:26|M
@W: CL112 :"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":108:2:108:3|M
@N: CL201 :"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":108:2:108:3|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":122:15:122:25|M
@W: :"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":122:15:122:25|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\led_flashing.vhd":7:7:7:18|M
@W: CD604 :"c:\actelprj\pa3_demoboard_72\hdl\led_flashing.vhd":39:6:39:19|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\mux2.vhd":5:7:5:10|M
@W: CD604 :"c:\actelprj\pa3_demoboard_72\hdl\mux2.vhd":23:6:23:19|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\my_clk_divider.vhd":6:7:6:17|M
@N: CD630 :"c:\actelprj\pa3_demoboard_72\hdl\top.vhd":9:7:9:9|M
@N: :"c:\actelprj\pa3_demoboard_72\hdl\top.vhd":10:7:10:9|M
@W: CG296 :"c:\actelprj\pa3_demoboard_72\hdl\top.vhd":106:16:106:22|M
@W: CD434 :"c:\actelprj\pa3_demoboard_72\hdl\top.vhd":106:24:106:26|M
@W: CG290 :"c:\actelprj\pa3_demoboard_72\hdl\top.vhd":109:3:109:5|M
@W: CG290 :"c:\actelprj\pa3_demoboard_72\hdl\top.vhd":128:14:128:19|M
