设计与验证verilog hdl
源代码在线查看： top.msg
@TM:1141839853
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1141839850
@N: :"c:\prj\example-4-21\syn_wr\decode.v":3:7:3:12|Synthesizing module decode
@TM:1141840106
@W: BN116 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@TM:1141840105
@W: CL113 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL113 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL113 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@TM:1141839850
@W: CL118 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL118 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL118 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@TM:1141840106
@W: FO108 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@TM:1141839850
@N: :"c:\prj\example-4-21\syn_wr\read_reg.v":2:7:2:14|Synthesizing module read_reg
@N: :"c:\prj\example-4-21\syn_wr\top.v":1:7:1:9|Synthesizing module top
@N: :"c:\prj\example-4-21\syn_wr\write_reg.v":2:7:2:15|Synthesizing module write_reg
@TM:1141840106
@W: BN116 :"c:\prj\example-4-21\syn_wr\write_reg.v":9:2:9:7|M
@TM:1141839850
@N: CG179 :"c:\prj\example-4-21\syn_wr\write_reg.v":29:29:29:32|M
@N: CG179 :"c:\prj\example-4-21\syn_wr\write_reg.v":30:29:30:32|M
@N: CG179 :"c:\prj\example-4-21\syn_wr\write_reg.v":31:29:31:32|M
