FPGA读SRAM中的数再传给CY7C68013
源代码在线查看： top.mrp
Release 6.2i Map G.28 Xilinx Mapping Report File for Design 'top' Design Information ------------------ Command Line : D:/install/Xilinx/bin/nt/map.exe -intstyle ise -p
xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd
top.pcf Target Device : x3s400 Target Package : pq208 Target Speed : -4 Mapper Version : spartan3 -- $Revision: 1.16.8.1 $ Mapped Date : Fri Dec 15 10:43:39 2006 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 68 out of 7,168 1% Number of 4 input LUTs: 76 out of 7,168 1% Logic Distribution: Number of occupied Slices: 60 out of 3,584 1% Number of Slices containing only related logic: 60 out of 60 100% Number of Slices containing unrelated logic: 0 out of 60 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 101 out of 7,168 1% Number used as logic: 76 Number used as a route-thru: 25 Number of bonded IOBs: 45 out of 141 31% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 1,153 Additional JTAG gate count for IOBs: 2,160 Peak Memory Usage: 74 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information Section 13 - Additional Device Resource Counts Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic. INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP) Section 4 - Removed Logic Summary --------------------------------- 8 block(s) removed 2 block(s) optimized away Section 5 - Removed Logic ------------------------- Unused block "data_SRAM_0_IOBUF/OBUFT" (TRI) removed. Unused block "data_SRAM_1_IOBUF/OBUFT" (TRI) removed. Unused block "data_SRAM_2_IOBUF/OBUFT" (TRI) removed. Unused block "data_SRAM_3_IOBUF/OBUFT" (TRI) removed. Unused block "data_SRAM_4_IOBUF/OBUFT" (TRI) removed. Unused block "data_SRAM_5_IOBUF/OBUFT" (TRI) removed. Unused block "data_SRAM_6_IOBUF/OBUFT" (TRI) removed. Unused block "data_SRAM_7_IOBUF/OBUFT" (TRI) removed. Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | CE_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | LB_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | OE_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | UB_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | WE_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | addr_SRAM | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | clk | IOB | INPUT | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | data_SRAM | IOB | BIDIR | LVCMOS25 | | | | | | | fifoaddr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifoaddr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | fifodata | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | full_flag | IOB | INPUT | LVCMOS25 | | | | | | | led | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | pktend | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | reset | IOB | INPUT | LVCMOS25 | | | | | | | slwr | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group Summary ------------------------------ No area groups were found in this design. Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design. Section 11 - Timing Report -------------------------- This design was not run using timing mode. Section 12 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 13 - Additional Device Resource Counts ---------------------------------------------- Number of JTAG Gates for IOBs = 45 Number of Equivalent Gates for Design = 1,153 Number of RPM Macros = 0 Number of Hard Macros = 0 DCIRESETs = 0 CAPTUREs = 0 BSCANs = 0 STARTUPs = 0 DCMs = 0 GCLKs = 1 ICAPs = 0 18X18 Multipliers = 0 Block RAMs = 0 Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 13 IOB Dual-Rate Flops not driven by LUTs = 0 IOB Dual-Rate Flops = 0 IOB Slave Pads = 0 IOB Master Pads = 0 IOB Latches not driven by LUTs = 0 IOB Latches = 0 IOB Flip Flops not driven by LUTs = 0 IOB Flip Flops = 0 Unbonded IOBs = 0 Bonded IOBs = 45 Shift Registers = 0 Static Shift Registers = 0 Dynamic Shift Registers = 0 16x1 ROMs = 0 16x1 RAMs = 0 32x1 RAMs = 0 Dual Port RAMs = 0 MUXFXs = 0 MULTANDs = 0 4 input LUTs used as Route-Thrus = 25 4 input LUTs = 76 Slice Latches not driven by LUTs = 0 Slice Latches = 0 Slice Flip Flops not driven by LUTs = 13 Slice Flip Flops = 68 SliceMs = 0 SliceLs = 60 Slices = 60 Number of LUT signals with 4 loads = 0 Number of LUT signals with 3 loads = 1 Number of LUT signals with 2 loads = 2 Number of LUT signals with 1 load = 67 NGM Average fanout of LUT = 2.04 NGM Maximum fanout of LUT = 23 NGM Average fanin for LUT = 3.5263 Number of LUT symbols = 76 Number of IPAD symbols = 3 Number of IBUF symbols = 11 Number of BIPAD symbols = 8
