FPGA-CPLD_DesignTool,事例程序1-2
源代码在线查看： top.mrp
Release 5.1i - Map F.23 Xilinx Mapping Report File for Design 'top' Design Information ------------------ Command Line : J:/eda/Xilinx/bin/nt/map.exe -quiet -p xc2vp50-ff1152-6 -cm
area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf Target Device : x2vp50 Target Package : ff1152 Target Speed : -6 Mapper Version : virtex2p -- $Revision: 1.4 $ Mapped Date : Wed Nov 06 17:38:36 2002 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Number of Slices containing unrelated logic: 0 out of 0 0% Number of bonded IOBs: 76 out of 692 10% Number of Block RAMs: 1 out of 232 1% Number of GCLKs: 2 out of 16 12% Total equivalent gate count for design: 65,542 Additional JTAG gate count for IOBs: 3,648 Peak Memory Usage: 155 MB Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group Summary Section 10 - Modular Design Summary Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "clka_BUFGP" (output signal=clka_BUFGP), BUFGP symbol "clkb_BUFGP" (output signal=clkb_BUFGP) INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND dpram_inst/GND VCC dpram_inst/VCC Section 6 - IOB Properties -------------------------- +------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | addra | IOB | INPUT | LVCMOS25 | | | | | | | addra | IOB | INPUT | LVCMOS25 | | | | | | | addra | IOB | INPUT | LVCMOS25 | | | | | | | addra | IOB | INPUT | LVCMOS25 | | | | | | | addrb | IOB | INPUT | LVCMOS25 | | | | | | | addrb | IOB | INPUT | LVCMOS25 | | | | | | | addrb | IOB | INPUT | LVCMOS25 | | | | | | | addrb | IOB | INPUT | LVCMOS25 | | | | | | | clka | IOB | INPUT | LVCMOS25 | | | | | | | clkb | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dina | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | dinb | IOB | INPUT | LVCMOS25 | | | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | douta | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | doutb | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | | wea | IOB | INPUT | LVCMOS25 | | | | | | | web | IOB | INPUT | LVCMOS25 | | | | | | +------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group Summary ------------------------------ No area groups were found in this design. Section 10 - Modular Design Summary ----------------------------------- Modular Design not used for this design.
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