设计与验证verilog hdl

				@P:  Worst Slack : -0.475
				@P:  syn_rst|clk - Estimated Frequency : 315.5 MHz
				@P:  syn_rst|clk - Requested Frequency : 371.2 MHz
				@P:  syn_rst|clk - Estimated Period : 3.169
				@P:  syn_rst|clk - Requested Period : 2.694
				@P:  syn_rst|clk - Slack : -0.475