设计与验证verilog hdl

				@P:  Worst Slack : -0.484
				@P:  state2_default|clk - Estimated Frequency : 309.6 MHz
				@P:  state2_default|clk - Requested Frequency : 364.2 MHz
				@P:  state2_default|clk - Estimated Period : 3.230
				@P:  state2_default|clk - Requested Period : 2.745
				@P:  state2_default|clk - Slack : -0.484