设计与验证verilog hdl

				#-- Synplicity, Inc.
				#-- Version Synplify Pro 8.1
				#-- Project file C:\prj\FSM_abc\state1\state1.prd
				#-- Written on Fri Dec 16 14:50:01 2005
				
				#
				### Watch Implementation type ###
				#
				watch_impl -all
				#
				### Watch Implementation properties ###
				#
				watch_prop -clear {  state1|clk - Estimated Frequency }