设计与验证verilog hdl

				#-- Synplicity, Inc.
				#-- Version Synplify Pro 8.1
				#-- Project file C:\prj\Example-4-21\asyn_bad\asyn_bad.prd
				#-- Written on Thu Mar 09 02:05:10 2006
				
				#
				### Watch Implementation type ###
				#
				watch_impl -all
				#
				### Watch Implementation properties ###
				#
				watch_prop -clear