module half_adder(a,b,out,carry); input a,b; output out,carry; assign {carry,out}=a+b; endmodule
http://www.codebf.com/read/13605/279608
module mux8x8(a,b,out); parameter size=8,longsize=16; input [size-1:0]a,b; output [longsize-1:0]out; reg [size-1:0]opa,opb; reg [longsize:1]result ; reg [size:0]n; reg [longsize-1:0]out; always
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`timescale 1ns/1ps module mult_piped_8x8_2sC(a,b,clk,reset,y); input [7:0]a,b; input clk,reset; output [15:0] y; reg[7:0] aR [8:0]; reg[7:0] bR [8:0]; reg[15:0]yR [8:0]; always@(posedge clk)
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module s_adder(a,b,c_in,sum,c_out); parameter length=16; input [length-1:0] a,b; input c_in; output c_out; output [length-1:0] sum; wire [length:1] c; full_adder p0 (a[0
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module lead_8bits_adder(a,b,cin,sum,cout); input [7:0]a,b; input cin; output [7:0]sum; output cout; reg [7:0]sum; reg cout; always@(a or b or cin) begi
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module mult_select(a,b,select,out); parameter size=8; input [size-1:0]a,b; input select; output [size-1:0]out; reg [size-1:0]out; always@(a or b or select) begin if(sel
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module compare(a,b,equal); parameter size=1; input [size-1:0]a,b; output equal; assign equal=(a==b)?1:0; endmodule
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`include "cla_8bits.v" module test_cla_8bits; reg [7:0] m,n; reg cin; wire [7:0] sum; wire cout; cla_8bits tt (m,n,cin,cout,sum); initial begin #40 cin= 1;
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module fifo(clock,reset,read,write,fifo_in,fifo_out,fifo_empty,fifo_half,fifo_full); input clock,reset,read,write; input [15:0] fifo_in; output [15:0] fifo_out; output
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http://www.codebf.com/read/13605/279619
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