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tb_sdrtest.v

//testbench for vgasdram `timescale 1ns/1ns module tb_sdrtest; /* sdram sd_model( .clk(sdram_clk), .csb(sdram_cs_n), .cke(sdram_cke), .ba(sdram_ba), .ad(sdram_addr), .r

http://www.codebf.com/read/11637/231943
cyclone_atoms.v

// Copyright (C) 1991-2008 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any o

http://www.codebf.com/read/11637/231944
sdrsd50_071010.v

/*================================================================== * Copyright(c) Samsung Electronics Co., 1997,1998. All rights reseved. * * Verilog Behavioral Model of Synchronous DRAM * * D

http://www.codebf.com/read/11637/231945
sdr_test.v

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company : // Engineer : // Create Date : // Design Name : // Module Name : sdr_test

http://www.codebf.com/read/11637/231947
pll_ctrl.v

// megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // File Name: PLL_ctrl.v // Megafu

http://www.codebf.com/read/11637/231948
sdram_cmd.v

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company : // Engineer : // Create Date : // Design Name : // Module Name : sdram_cmd

http://www.codebf.com/read/11637/231949
sdr_para.v

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company : // Engineer : 特权 franchises3 // Create Date : 2009.05.11 // Design Name : /

http://www.codebf.com/read/11637/231951
sdfifo_ctrl.v

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company : // Engineer : // Create Date : // Design Name : // Module Name : sdfifo_c

http://www.codebf.com/read/11637/231958
rdfifo_bb.v

// megafunction wizard: %FIFO%VBB% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: dcfifo // ============================================================ // File Name: rdfifo.v // Megafu

http://www.codebf.com/read/11637/231960
datagene.v

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company : // Engineer : // Create Date : // Design Name : // Module Name : datagene

http://www.codebf.com/read/11637/231962

搜索结果： 系统搜索到约有7641项符合V的查询结果

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搜索结果：系统搜索到约有7641项符合V的查询结果