关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
...
/dl/179429.html
标签：
investigates
implementing
pipelines
circuits
上传时间：
2015-07-26
上传用户：CHINA526
