Verilog and VHDL状态机设计，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a var ...
Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces between synchronous and asynchronous systems, or between
synchronous systems operating from different clocks.
This paper presents several low-latency mixed-timing
FIFO (first-in–first-out) interfaces designs that interface systems
on a chip working at different speeds. The connected systems
can be either synchronous or asynchronous. The designs are then
adapted to work between systems with very long interc ...
Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double synchronous serial ports (I² C™ and SPI™ ) and double asynchronous (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program ...
vhdl编写，8b—10b 编解码器设计
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
Asynchronous active high reset initializes all logic
Encoded data output
...
The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero, generates the flute when the posedge, MD_Counter8One,generates the flute when the negedge.The aim of the module is to generate the mended miller code to be the source of the MillerDecode.
输入的数据以 ...
This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent synchronous implementation in the same technology. The chip is fully bit compatible with the sync ...
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
-- Shift direction: right/left (right active high)
--
-- CLK active : high
-- CLR active : high
-- CLR type : synchronous
-- SET active : high
-- SET type : synchronous
-- LOAD active : high
-- CE active : high
-- SERIAL input : SI ...
CRC码产生器与校验器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or asynchronous reset
In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for uniformly quantized synchronous code division multiple access (CDMA) signals in additive white Gaussian noise (AWGN) channels.This project is mainly based on the representation of uniform quantizer by ...
