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基于（英蓓特）STM32V100的串口程序

This example provides a description of how  to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypa ...

/dl/37358.html

标签： V100 STM 100 32V

上传时间： 2013-10-31

上传用户：yy_cn

Xilinx UltraScale：新一代架构满足您的新一代架构需求（EN）

　　中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html 　　Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture 　　The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class ...

/dl/38746.html

标签： UltraScale Xilinx 架构

上传时间： 2013-11-21

上传用户：wxqman

WP151 - Xilinx FPGA的System ACE配置解决方案

Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bo ...

/dl/40068.html

标签： System Xilinx FPGA 151

上传时间： 2013-11-23

上传用户：kangqiaoyibie

WP401-FPGA设计的DO-254

The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard ...

/dl/40071.html

标签： FPGA 401 254 WP

上传时间： 2013-11-03

上传用户：ysystc670

WP247 - Virtex-5系列高级封装

The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect ofdesign that plays an increasingly important role isthat o ...

/dl/40072.html

标签： Virtex 247 WP 高级封装

上传时间： 2013-11-07

上传用户：wanghui2438

Verilog编码中的非阻塞性赋值

  One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...

/dl/40125.html

标签： Verilog 编码非阻塞性赋值

上传时间： 2013-11-01

上传用户：xzt

通信的数学理论

The fundamental problem of communication is that of reproducing at one point either exactly or approximately a message selected at another point. Frequently the messages have meaning; that is they refer to or are correlated according to some system with certain physical or conceptual entities.

/dl/40145.html

标签： 通信

上传时间： 2013-11-11

上传用户：xy@1314

Design Safe Verilog State Machine（Synplicity）

  One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...

/dl/40146.html

标签： Synplicity Machine Verilog Design

上传时间： 2013-10-20

上传用户：苍山观海

VHDL,Verilog,System verilog比较

  本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers ...

/dl/40147.html

标签： Verilog verilog System VHDL

上传时间： 2014-03-03

上传用户：zhtzht

CPLD和FPGA设计介绍

Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system ...

/dl/40148.html

标签： CPLD FPGA

上传时间： 2013-10-22

上传用户：lmq0059

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ONE 884条

按分类查找:

基于（英蓓特）STM32V100的串口程序

Xilinx UltraScale：新一代架构满足您的新一代架构需求（EN）

WP151 - Xilinx FPGA的System ACE配置解决方案

WP401-FPGA设计的DO-254

WP247 - Virtex-5系列高级封装

Verilog编码中的非阻塞性赋值

通信的数学理论

Design Safe Verilog State Machine（Synplicity）

VHDL,Verilog,System verilog比较

CPLD和FPGA设计介绍

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