NAME: u2440mon.c
DESC: u2440mon entry point,menu,download
HISTORY:
Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2410X.
Mar.27.2002:purnnamu: DMA is enabled.
Apr.01.2002:purnnamu: isDownloadReady flag is added.
Apr.10.2002:purnnamu: - Selecting menu is available in the waiting loop ...
ADM6993F/FXFiber to Fast Ethernet Converter (TS1000 CPE Complied)
The ADM6993F/FX is a single chip integrating two 10/100 Mbps MDIX TX/FX transceivers, a three-port 10/100M Ethernet L2 switch controller, and one OAM engine to meet demanding applications, including Fiber-to-Ethernet media converters, ...
This GLib version 2.16.1. GLib is the low-level core
library that forms the basis for projects such as GTK+ and GNOME. It
provides data structure handling for C, portability wrappers, and
interfaces for such runtime functionality as an event loop, threads,
dynamic loading, and an object system.
DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Dig ...
A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he comp en2
sation cur rent int o t he p assive loop f ilte r during t he delay time of t he p hase f requency detect or ( PFD) , a maximum
reduction of t he p hase noise by about 16dB can be achieved. ...
This document describes how to switch to and program the unisersal serial bus (USB)
analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example
assembly programs for programming and switching to and from the APLL are also
provided in the attached zip file. It is assumed that the reade ...
