标签：INTERFACE - 电子研发网

INTERFACE 949条

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基于USB接口的数据采集模块的设计与实现

基于USB接口的数据采集模块的设计与实现Design and Implementation of USB-Based Data Acquisition Module路永伸(天津科技大学电子信息与自动化学院，天津300222)摘要文中给出基于USB接口的数据采集模块的设计与实现。硬件设计采用以Adpc831与PDIUSBDI2为主的器件进行硬件设计，采用Windriver开发USB驱动，并用Visual C十 ...

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标签： USB 接口数据采集模块

上传时间： 2013-10-23

上传用户：q3290766

Create a 1-Wire Master with Xilinx PicoBlaze

Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wir ...

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标签： PicoBlaze Create Master Xilinx

上传时间： 2013-11-05

上传用户：a6697238

AN522: Implementing Bus LVDS

This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.

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标签： Implementing LVDS 522 Bus

上传时间： 2013-11-10

上传用户：frank1234

xapp069 - 使用XC9500 JTAG边界扫描接口

This application note explains the XC9500™/XL/XV Boundary Scan interface anddemonstrates the software available for programming and testing XC9500/XL/XV CPLDs. Anappendix summarizes the iMPACT software operations and provides an overview of theadditional operations supported by XC9500/XL/XV ...

/dl/32569.html

标签： xapp 9500 JTAG 069

上传时间： 2013-11-15

上传用户：fengweihao158@163.com

XAPP424 - 嵌入式JTAG ACE播放器

This application note contains a reference design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing desi ...

/dl/32583.html

标签： XAPP JTAG 424 ACE

上传时间： 2013-11-14

上传用户：JIMMYCB001

PLB Block RAM(BRAM)接口控制器

The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).

/dl/32604.html

标签： Block BRAM PLB RAM

上传时间： 2013-10-27

上传用户：zoudejile

基于Xilinx FPGA的双输出DC/DC转换器解决方案

  Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The ...

/dl/32612.html

标签： Xilinx FPGA DC 输出

上传时间： 2013-10-22

上传用户：liu999666

XAPP740利用AXI互联设计高性能视频系统

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX  and area optimizat ...

/dl/32619.html

标签： XAPP 740 AXI 互联

上传时间： 2013-11-14

上传用户：fdmpy

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接  The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and ...

/dl/32622.html

标签： XAPP FPGA Bank 520

上传时间： 2013-11-19

上传用户：yyyyyyyyyy

Virtex-5 GTP Transceiver Wizar

The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standa ...

/dl/32709.html

标签： Transceiver Virtex Wizar GTP

上传时间： 2013-10-23

上传用户：leyesome

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INTERFACE 949条

按分类查找:

基于USB接口的数据采集模块的设计与实现

Create a 1-Wire Master with Xilinx PicoBlaze

AN522: Implementing Bus LVDS

xapp069 - 使用XC9500 JTAG边界扫描接口

XAPP424 - 嵌入式JTAG ACE播放器

PLB Block RAM(BRAM)接口控制器

基于Xilinx FPGA的双输出DC/DC转换器解决方案

XAPP740利用AXI互联设计高性能视频系统

XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接

Virtex-5 GTP Transceiver Wizar

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