@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":9:7:9:9|Synthesizing work.top.def_arch
@W: CD434 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":106:24:106:26|Signal sw2 in the sensitivity list is
-- VHDL model created from schematic top.sch -- Apr 19 17:36:39 2003
LIBRARY vanmacro;
USE vanmacro.components.ALL;
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeri
