@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":9:7:9:9|Synthesizing work.top.def_arch
@W: CD434 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":106:24:106:26|Signal sw2 in the sensitivity list is not used in the process
@W: CG296 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":106:16:106:22|Incomplete sensitivity list - assuming completeness
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":109:3:109:5|Referenced variable sw1 is not in sensitivity list
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Top.vhd":128:14:128:19|Referenced variable lcd_en is not in sensitivity list
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":9:7:9:9|Synthesizing work.lcd.behavioural
@N: CD231 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":23:16:23:17|Using onehot encoding for type state_type (warmup="100000000")
@W: CD604 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":101:12:101:26|OTHERS clause is not synthesized
Post processing for work.lcd.behavioural
@W: CL112 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Feedback mux created for signal lcd_data[7:4]. Did you forget the set/reset assignment for this signal?
@W: CL112 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Feedback mux created for signal finished. Did you forget the set/reset assignment for this signal?
@W: CL112 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Feedback mux created for signal lcd_rs. Did you forget the set/reset assignment for this signal?
@N: CL201 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_to_LCD.vhd":108:2:108:3|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 9 reachable states with original encodings of:
000000001
000000010
000000100
000001000
000010000
000100000
001000000
010000000
100000000
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\my_clk_divider.vhd":6:7:6:17|Synthesizing work.clk_divider.def_arch
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\clockdiv.vhd":5:7:5:14|Synthesizing work.clockdiv.behavioural
Post processing for work.clockdiv.behavioural
Post processing for work.clk_divider.def_arch
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\Data_block.vhd":8:7:8:16|Synthesizing work.data_block.def_arch
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\mux2.vhd":5:7:5:10|Synthesizing work.mux2.behavioral
@W: CD604 :"C:\Actelprj\PA3_DemoBoard_72\hdl\mux2.vhd":23:6:23:19|OTHERS clause is not synthesized
Post processing for work.mux2.behavioral
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":6:7:6:12|Synthesizing work.count8.behavioral
@W: CG296 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":21:2:21:8|Incomplete sensitivity list - assuming completeness
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":27:23:27:26|Referenced variable data is not in sensitivity list
@W: CG290 :"C:\Actelprj\PA3_DemoBoard_72\hdl\count8.vhd":26:11:26:15|Referenced variable sload is not in sensitivity list
Post processing for work.count8.behavioral
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\LED_Flashing.vhd":7:7:7:18|Synthesizing work.led_flashing.behavioral
@W: CD604 :"C:\Actelprj\PA3_DemoBoard_72\hdl\LED_Flashing.vhd":39:6:39:19|OTHERS clause is not synthesized
@N: CD630 :"C:\Actelprj\PA3_DemoBoard_72\hdl\binary_counter.vhd":6:7:6:20|Synthesizing work.binary_counter.behavioral
Post processing for work.binary_counter.behavioral
Post processing for work.led_flashing.behavioral
Post processing for work.data_block.def_arch
Post processing for work.top.def_arch
