曼彻斯特编解码Verilog代码.zip
源代码在线查看： me_tf.v
`timescale 1 ns / 1 ns module me_tf ; reg [7:0] din ; reg rst ; reg clk ; reg wr ; wire mdo ; wire ready ; me u1 (rst,clk,wr,din,ready,mdo) ; initial begin rst = 1'b0 ; clk = 1'b0 ; din = 8'h0 ; wr = 1'b0 ; me.clk1 = 1'b0 ; me.count = 3'b0 ; end integer me_chann ; initial begin me_chann = $fopen("me.rpt") ; $timeformat(-9,,,5) ; end parameter clock_period = 10 ; setup_time = clock_period/4 ; always #(clock_period/2) clk = ~clk ; initial begin $fdisplay(me_chann, "Verilog simulation of Manchester encoder\n\n:); $shm_open("me.shm") ; $shm_probe("AS") ; $fmonitor(me_chann,"%ime=%t,rst=%b,wr=%b,me.clk=%b,din=%h,me.count=%b,mdo=%b,ready=%b",$time,rst,wr,clk,me.clk1,din,me.count,mdo,ready) ; #5 rst = 1'b1; #15 rst = 1'b0 ; #(3 * clock_period - setup_time) din = 8'hff ; #(1 * clock_period) wr = 1'b1 ; #(1 * clock_period) wr = 1'b0 ; #(20 * clock_period) din = 8'haa ; #(1 * clock_period) wr = 1'b1 ; #(1 * clock_period) wr = 1'b0 ; #(20 * clock_period) din = 8'h00 ; #(1 * clock_period) wr = 1'b1 ; #(1 * clock_period) wr = 1'b0 ; #(20 * clock_period) din = 8'hf0 ; #(1 * clock_period) wr = 1'b1 ; #(1 * clock_period) wr = 1'b0 ; #(20 * clock_period) din = 8'h0f ; #(1 * clock_period) wr = 1'b1 ; #(1 * clock_period) wr = 1'b0 ; #(100 * clock_period) ; $fdisplay (me_chann,"\nSimulation of Manchester encoder complete."); $finish ; end endmodule
