NANDFlashController.zip

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				//-------------------------------------------------------------------------
				//  >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE 				//-------------------------------------------------------------------------
				//  Copyright (c) 2009 by Lattice Semiconductor Corporation      
				// 
				//-------------------------------------------------------------------------
				// Permission:
				//
				//   Lattice Semiconductor grants permission to use this code for use
				//   in synthesis for any Lattice programmable logic product.  Other
				//   use of this code, including the selling or duplication of any
				//   portion is strictly prohibited.
				//
				// Disclaimer:
				//
				//   This VHDL or Verilog source code is intended as a design reference
				//   which illustrates how these types of functions can be implemented.
				//   It is the user's responsibility to verify their design for
				//   consistency and functionality through the use of formal
				//   verification methods.  Lattice Semiconductor provides no warranty
				//   regarding the use or functionality of this code.
				//-------------------------------------------------------------------------
				//
				//    Lattice Semiconductor Corporation
				//    5555 NE Moore Court
				//    Hillsboro, OR 97124
				//    U.S.A
				//
				//    TEL: 1-800-Lattice (USA and Canada)
				//    503-268-8001 (other locations)
				//
				//    web: http://www.latticesemi.com/
				//    email: techsupport@latticesemi.com
				// 
				//-------------------------------------------------------------------------
				//
				// Revision History :
				// --------------------------------------------------------------------
				//   Ver  :| Author :| Mod. Date :| Changes Made:
				//   v01.0:| J.T    :| 06/20/09  :| Initial ver
				// --------------------------------------------------------------------
				//
				// 
				//Description of module:
				//--------------------------------------------------------------------------------
				// 
				// --------------------------------------------------------------------
				`timescale 1 ns / 1 fs
				
				module nfcm_tb();
				
				 reg clk,rst;
				// reg [7:0] DIO_reg;
				// reg ena;
				 wire [7:0] DIO;
				 wire CLE;// -- CLE
				 wire ALE;//  -- ALE
				 wire WE_n;// -- ~WE
				 wire RE_n; //-- ~RE
				 wire CE_n; //-- ~CE
				 wire R_nB; //-- R/~B
				
				 reg BF_sel;
				 reg [10:0] BF_ad;
				 reg [7:0] BF_din;
				 reg BF_we;
				 reg [15:0] RWA; //-- row addr
				 wire [7:0] BF_dou;
				
				 wire PErr ; // -- progr err
				 wire EErr ; // -- erase err
				 wire RErr ;
				
				 reg [2:0] nfc_cmd; // -- command see below
				 reg nfc_strt;//  -- pos edge (pulse) to start
				 wire nfc_done;//  -- operation finished if '1'
				
				  
				reg[7:0] memory[0:2047];
				
				reg [7:0] temp;
				  
				GSR GSR_INST(.GSR(1'b1));
				PUR PUR_INST(.PUR(1'b1));  
				
				parameter period=16;         // suppose 60MHz
				
				//assign DIO=ena?DIO_reg:8'hzz;
				initial begin
				  clk 					rst  					BF_sel					BF_ad					BF_din					BF_we					RWA					nfc_cmd					nfc_strt					temp				//	R_nB				//	DIO_reg				//	ena					#300;
					rst				
					kill_time; 
					kill_time; 
				
					reset_cycle;
				
					kill_time; 
					kill_time; 
					
					erase_cycle(16'h1234);
					
					kill_time; 
					kill_time;
					
					write_cycle(16'h1234);
					
					kill_time; 
					kill_time;
					
					read_cycle(16'h1234);
					
					kill_time; 
					kill_time;
				
					read_id_cycle(16'h0000);
					
					kill_time; 
					kill_time;
					
				        #1000;
					$stop;
					
					end
				
				always
				   #(period/2) clk 				   
				// Instantiation of the nfcm
				nfcm_top nfcm(
				 .DIO(DIO),
				 .CLE(CLE),
				 .ALE(ALE),
				 .WE_n(WE_n),
				 .RE_n(RE_n),
				 .CE_n(CE_n),
				 .R_nB(R_nB),
				
				 .CLK(clk),
				 .RES(rst),
				
				 .BF_sel(BF_sel),
				 .BF_ad (BF_ad ),
				 .BF_din(BF_din),
				 .BF_we (BF_we ),
				 .RWA   (RWA   ), 
				
				 .BF_dou(BF_dou),
				 .PErr(PErr), 
				 .EErr(EErr), 
				 .RErr(RErr),
				      
				 .nfc_cmd (nfc_cmd ), 
				 .nfc_strt(nfc_strt),  
				 .nfc_done(nfc_done)
				);
				
				// Instantiation of the nand flash interface
				flash_interface nand_flash(
				    .DIO(DIO),
				    .CLE(CLE),// -- CLE
				    .ALE(ALE),//  -- ALE
				    .WE_n(WE_n),// -- ~WE
				    .RE_n(RE_n), //-- ~RE
				    .CE_n(CE_n), //-- ~CE
				    .R_nB(R_nB), //-- R/~B
				    .rst(rst)
				);
				
				// --------------------------------------------------------------------
				// --------------------------------------------------------------------
				// erase block task
				// NFC commands (all remaining encodings are ignored = NOP):
				//-- WPA 001=write page
				//-- RPA 010=read page
				//-- EBL 100=erase block
				//-- RET 011=reset
				//-- RID 101= read ID
				task reset_cycle;    
				begin
				    @(posedge clk) ;
				//    RWA=address;
				    nfc_cmd=3'b011;
				    nfc_strt=1'b1;
				
				    @(posedge clk) ;
				    nfc_strt=1'b0;    
				   wait(nfc_done);
				   @(posedge clk) ;
				   nfc_cmd=3'b111;                                           
				   $display($time,"  %m  \t \t  >"); 
				    
				end      
				endtask 
				
				
				task erase_cycle;
				    input [15:0]  address; 
				begin
				//    $display($time,"  %m  \t \t  >",address);
				    @(posedge clk) ;
				    #3;
				    RWA=address;
				    nfc_cmd=3'b100;
				    nfc_strt=1'b1;
				
				    @(posedge clk) ;
				    #3;
				    nfc_strt=1'b0; 
				    @(posedge clk) ;
				
				   wait(nfc_done);
				   @(posedge clk) ;
				   nfc_cmd=3'b111;
				
				   if(EErr)                                         
				     $display($time,"  %m  \t \t  >");    
				   else                                             
				     $display($time,"  %m  \t \t  >"); 
				    
				end      
				endtask 
				// --------------------------------------------------------------------
				// --------------------------------------------------------------------
				// write page task
				// NFC commands (all remaining encodings are ignored = NOP):
				//-- WPA 001=write page
				//-- RPA 010=read page
				//-- EBL 100=erase block
				
				task write_cycle;
				    input [15:0]  address; 
				    integer i;
				begin
				//    $display($time,"  %m  \t \t  >",address);
				    @(posedge clk) ;
				    #3;
				    RWA=address;
				    nfc_cmd=3'b001;
				    nfc_strt=1'b1;
				    BF_sel=1'b1;
				    @(posedge clk) ;
				    #3;
				    nfc_strt=1'b0; 
				    BF_ad=0;
				    for(i=0;i				       @(posedge clk) ; 
				       #3;      
				       BF_we=1'b1;
				       memory[i]=$random % 256; 
				       BF_din				       BF_ad				    end 
				   @(posedge clk) ;
				   @(posedge clk) ;
				   #3;
				   BF_we=1'b0;  
				   wait(nfc_done);
				   @(posedge clk) ;
				   #3;
				   nfc_cmd=3'b111;
				   BF_sel=1'b0;
				   if(PErr)                                         
				     $display($time,"  %m  \t \t  >");    
				   else                                             
				     $display($time,"  %m  \t \t  >"); 
				    
				end      
				endtask 
				
				// --------------------------------------------------------------------
				// --------------------------------------------------------------------
				// read page task
				// NFC commands (all remaining encodings are ignored = NOP):
				//-- WPA 001=write page
				//-- RPA 010=read page
				//-- EBL 100=erase block
				task read_cycle;
				    input [15:0]  address; 
				    integer i;
				    
				begin
				    @(posedge clk) ;
				    #3;
				    RWA=address;
				    nfc_cmd=3'b010;
				    nfc_strt=1'b1;
				    BF_sel=1'b1;
				    BF_we=1'b0;
				    BF_ad=#3 0;
				    @(posedge clk) ;
				    #3;
				    nfc_strt=1'b0;  
				    @(posedge clk) ;  
				   wait(nfc_done);
				   @(posedge clk) ;
				   #3;
				   nfc_cmd=3'b111;
				   BF_ad				   for(i=0;i				       @(posedge clk) ;
				       temp				       BF_ad				    end 
				   
				   if(RErr)                                         
				     $display($time,"  %m  \t \t  >");    
				   else                                             
				     $display($time,"  %m  \t \t  >"); 
				    
				end      
				endtask 
				
				
				task read_id_cycle;
				    input [15:0]  address; 
				    
				begin
				    @(posedge clk) ;
				    #3;
				    RWA=address;
				    nfc_cmd=3'b101;
				    nfc_strt=1'b1;
				    BF_sel=1'b1;
				    @(posedge clk) ;
				    #3;
				    nfc_strt=1'b0;    
				    @(posedge clk) ;
				   wait(nfc_done);
				   @(posedge clk) ;
				   nfc_cmd=3'b111;
				      $display($time,"  %m  \t \t  >"); 
				    
				end      
				endtask 
				
				
				
				// -------------------------------------------------------------------- 
				// Task for waiting                                                     
				                                                                        
				task kill_time;                                                         
				  begin                                                                 
				    @(posedge clk);                                                 
				    @(posedge clk);                                                 
				    @(posedge clk);                                                 
				    @(posedge clk);                                                 
				    @(posedge clk);                                                 
				  end                                                                   
				endtask // of kill_time;                                                
				                                                                        
				// ---------------------------------------------------------------------   
				
				 
				endmodule
				
				
				
							

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