verilog代码集锦.rar

				module Test;				reg clock,updn;				wire[0:3]cnt_out;								countupdown c1(clock,cnt_out,updn);				always #1 clock=~clock;								initial begin				    clock=0;				   updn=0;				   #50 updn=1;				   #100 $dumpflush;				   $stop;				end								initial begin				   $dumpfile("count.dump");				   $dumplimit(4096);				   $dumpvars(0,Test);				   $dumpvars(0,c1.count,c1.clk,c1.up_down);				end				endmodule