verilog代码集锦.rar
源代码在线查看： machine.v
module machine(clk,reset,in,out); input clk,reset,in; output out; reg out; parameter set0=0,hold=1,set1=2; reg [1:0] state; always@(posedge clk or negedge reset) begin if(!reset) state else case(state) set0: state hold: if(in==0) state else state set1: state default state endcase end always@(state)begin case(state) set0:out=0; hold:out=0; set1:out=1; default: out=1'bz; endcase end endmodule `timescale 1ns/1ns module machine_tb; reg clk,reset,in; wire out; always #1 clk=~clk; machine c1(.clk(clk),.reset(reset),.in(in),.out(out)); initial begin clk=0; reset=1; in=0; #2 reset=0; #2 reset=1; #8 in=1; #8 in=0; #100 $dumpflush; $stop; end initial begin $dumpfile("machine.dump"); $dumplimit(4096); $dumpvars(0,machine_tb); $dumpvars(0,c1.clk,c1.reset,c1.in,c1.out); end endmodule
