verilog代码集锦.rar

				module countu3d5_tb;				    reg rst,clk,up,dn;				    reg [7:0]din;				    wire[7:0]dout;				    wire par,carry,borrow;				    				    initial din=8'b11010011;				    always #1 clk=~clk;				    				    initial begin				    	clk=0;				    	rst=1;				    	up=0;dn=0;				    	#2 rst=0;				    	#2 rst=1;				    	#4 dn=1;				    	#200 dn=0;up=1;				    	$monitor("At time%t,dout=%b,par=%b,carry=%b,borrow=%b",$time,dout,par,carry,borrow);				    	#500$stop;				    end				    countu3d5 h1(.rst(rst), .clk(clk), .up(up), .dn(dn), .din(din), .dout(dout), .par(par), .carry(carry), .borrow(borrow));				  endmodule