verilog代码集锦.rar

				module countupdown(clk,count,up_down);				input clk,up_down;				output[0:3]count;				reg[0:3]count;								initial count='d5;				always@(posedge clk)begin				   if(up_down)begin				       count=count+1;				       if(count>12)count=count+1;  				   end				   else begin				       count=count-1;				       if(count				   end				 end				 endmodule