SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口
源代码在线查看： smii_tx_fifo.v
`include "SD_defines.v" module sd_tx_fifo ( input [4-1:0] d, input wr, input wclk, output [4-1:0] q, input rd, output full, output empty, output [5:0] mem_empt, input rclk, input rst ); reg [4-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1]; reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o; wire ram_we; wire [4-1:0] ram_din; assign ram_we = wr & ~full; assign ram_din = d; always @ (posedge wclk) if (ram_we) ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] always @ (posedge wclk or posedge rst) if (rst) adr_i else if (ram_we) if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] adr_i[`FIFO_TX_MEM_ADR_SIZE-1] end else adr_i always @ (posedge rclk or posedge rst) if (rst) adr_o else if (!empty & rd) begin if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] adr_o[`FIFO_TX_MEM_ADR_SIZE-1] end else adr_o end //------------------------------------------------------------------ // Simplified version of the three necessary full-tests: // assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && // (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && // (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0])); //------------------------------------------------------------------ assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ; assign empty = (adr_i == adr_o) ; assign mem_empt = ( adr_i-adr_o); assign q = ram[adr_o[5:0]]; endmodule
