//----------------------------------------------------- // Design Name : uart // File Name : uart.v // Function : Simple UART // Coder : Deepak Kumar Tala //----------------------------------------------------- module uart ( reset , txclk , ld_tx_data , tx_data , tx_enable , tx_out , tx_empty , rxclk , uld_rx_data , rx_data , rx_enable , rx_in , rx_empty ); // Port declarations input reset ; input txclk ; input ld_tx_data ; input [7:0] tx_data ; input tx_enable ; output tx_out ; output tx_empty ; input rxclk ; input uld_rx_data ; output [7:0] rx_data ; input rx_enable ; input rx_in ; output rx_empty ; // Internal Variables reg [7:0] tx_reg ; reg tx_empty ; reg tx_over_run ; reg [3:0] tx_cnt ; reg tx_out ; reg [7:0] rx_reg ; reg [7:0] rx_data ; reg [3:0] rx_sample_cnt ; reg [3:0] rx_cnt ; reg rx_frame_err ; reg rx_over_run ; reg rx_empty ; reg rx_d1 ; reg rx_d2 ; reg rx_busy ; // UART RX Logic always @ (posedge rxclk or posedge reset) if (reset) begin rx_reg rx_data rx_sample_cnt rx_cnt rx_frame_err rx_over_run rx_empty rx_d1 rx_d2 rx_busy end else begin // Synchronize the asynch signal rx_d1 rx_d2 // Uload the rx data if (uld_rx_data) begin rx_data rx_empty end // Receive data only when rx is enabled if (rx_enable) begin // Check if just received start of frame if (!rx_busy && !rx_d2) begin rx_busy rx_sample_cnt rx_cnt end // Start of frame detected, Proceed with rest of data if (rx_busy) begin rx_sample_cnt // Logic to sample at middle of data if (rx_sample_cnt == 7) begin if ((rx_d2 == 1) && (rx_cnt == 0)) begin rx_busy end else begin rx_cnt // Start storing the rx data if (rx_cnt > 0 && rx_cnt < 9) begin rx_reg[rx_cnt - 1] end if (rx_cnt == 9) begin rx_busy // Check if End of frame received correctly if (rx_d2 == 0) begin rx_frame_err end else begin rx_empty rx_frame_err // Check if last rx data was not unloaded, rx_over_run end end end end end end if (!rx_enable) begin rx_busy end end // UART TX Logic always @ (posedge txclk or posedge reset) if (reset) begin tx_reg tx_empty tx_over_run tx_out tx_cnt end else begin if (ld_tx_data) begin if (!tx_empty) begin tx_over_run end else begin tx_reg tx_empty end end if (tx_enable && !tx_empty) begin tx_cnt if (tx_cnt == 0) begin tx_out end if (tx_cnt > 0 && tx_cnt < 9) begin tx_out end if (tx_cnt == 9) begin tx_out tx_cnt tx_empty end end if (!tx_enable) begin tx_cnt end end endmodule
