基于FPGA有限状态机的数据采集系统

				Fitter Status : Successful - Wed Mar 18 22:17:25 2009
				Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
				Revision Name : top
				Top-level Entity Name : top
				Family : Cyclone
				Device : EP1C6Q240C8
				Timing Models : Final
				Total logic elements : 67 / 5,980 ( 1 % )
				Total pins : 54 / 185 ( 29 % )
				Total virtual pins : 0
				Total memory bits : 0 / 92,160 ( 0 % )
				Total PLLs : 0 / 2 ( 0 % )