Release 10.1.01 Map K.34 (nt) Xilinx Map Application Log File for Design 'top' Design Information ------------------ Command Line : map -ise
D:/hdl_designs/cpu8088/website/web_cpu88/drigmorn1/ISE/Drigmorn1/Drigmorn1.ise
-intstyle ise -p xc3s500e-cp132-4 -timing -logic_opt off -ol high -t 1 -cm area
-pr off -k 4 -power off -o top_map.ncd top.ngd top.pcf Target Device : xc3s500e Target Package : cp132 Target Speed : -4 Mapper Version : spartan3e -- $Revision: 1.46.12.1 $ Mapped Date : Sat May 17 13:25:02 2008 Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Running timing-driven packing... Phase 1.1 Phase 1.1 (Checksum:99fac5) REAL time: 5 secs Phase 2.7 Phase 2.7 (Checksum:1312cfe) REAL time: 5 secs Phase 3.31 Phase 3.31 (Checksum:1c9c37d) REAL time: 5 secs Phase 4.2 . Phase 4.2 (Checksum:26259fc) REAL time: 5 secs Phase 5.30 Phase 5.30 (Checksum:2faf07b) REAL time: 5 secs Phase 6.8 ........................................ ............. ............................................................................. . ....................................................................................... ............... ............... ............... ............................................................... Phase 6.8 (Checksum:259c0da) REAL time: 30 secs Phase 7.5 Phase 7.5 (Checksum:42c1d79) REAL time: 30 secs Phase 8.18 Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 mins 12 secs Phase 9.5 Phase 9.5 (Checksum:55d4a77) REAL time: 1 mins 13 secs REAL time consumed by placer: 1 mins 13 secs CPU time consumed by placer: 1 mins 13 secs Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 8 Logic Utilization: Total Number Slice Registers: 959 out of 9,312 10% Number used as Flip Flops: 952 Number used as Latches: 7 Number of 4 input LUTs: 5,049 out of 9,312 54% Logic Distribution: Number of occupied Slices: 2,794 out of 4,656 60% Number of Slices containing only related logic: 2,794 out of 2,794 100% Number of Slices containing unrelated logic: 0 out of 2,794 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 5,117 out of 9,312 54% Number used as logic: 5,011 Number used as a route-thru: 68 Number used for Dual Port RAMs: 38 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 10 out of 92 10% IOB Flip Flops: 1 Number of RAMB16s: 20 out of 20 100% Number of BUFGMUXs: 1 out of 24 4% Number of MULT18X18SIOs: 1 out of 20 5% Peak Memory Usage: 273 MB Total REAL time to MAP completion: 1 mins 24 secs Total CPU time to MAP completion: 1 mins 23 secs Mapping completed. See MAP report file "top_map.mrp" for details.
