是一些很好的FPGA设计实例

				Fitter Status : Successful - Sun Feb 25 04:49:57 2007
				Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
				Revision Name : control
				Top-level Entity Name : control
				Family : ACEX1K
				Device : EP1K30QC208-2
				Timing Models : Final
				Total logic elements : 135 / 1,728 ( 8 % )
				Total pins : 29 / 147 ( 20 % )
				Total memory bits : 0 / 24,576 ( 0 % )
				Total PLLs : 0 / 1 ( 0 % )