次代码利用verilog HDL来描述的

				Fitter Status : Successful - Tue Apr 07 16:57:56 2009
				Quartus II Version : 7.0 Build 33 02/05/2007 SJ Web Edition
				Revision Name : top
				Top-level Entity Name : top
				Family : FLEX10K
				Device : EPF10K10TC144-4
				Timing Models : Final
				Total logic elements : 12 / 576 ( 2 % )
				Total pins : 2 / 102 ( 2 % )
				Total memory bits : 0 / 6,144 ( 0 % )