UART程序

				module generator(clk,rst,ce,bd_out,indicator);				    input clk,rst,ce;				    output bd_out,indicator;				    reg indicator;				    reg[15:0] count;				    				    assign bd_out=(count				    				    always @(posedge clk or negedge rst)				    if(!rst)				      begin				          count				          indicator				      end				      else if(ce)				      begin				           if(count=='d52)				           begin				               count				               indicator				           end				           else				           begin				               count				               indicator				           end				       end				       else				         begin				             count				             indicator				         end				         				 endmodule