LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case1 IS
PORT ( table_in:in std_logic_vector(3 downto 0);
table_out:out integer range -10 to 70);
END case1;
ARCHITECTURE behave OF case1 IS
BEGIN
PROCESS (table_in)
BEGIN
case table_in is
when "0000"=>table_out when "0001"=>table_out when "0010"=>table_out when "0011"=>table_out when "0100"=>table_out when "0101"=>table_out when "0110"=>table_out when "0111"=>table_out when "1000"=>table_out when "1001"=>table_out when "1010"=>table_out when "1011"=>table_out when "1100"=>table_out when "1101"=>table_out when "1110"=>table_out when "1111"=>table_out when others=>table_out
end case;
END PROCESS;
END behave;