用VHDL语言设计简单的CPU

				library ieee;
				use ieee.std_logic_1164.all;
				use ieee.std_logic_unsigned.all;
				
				entity mbr is
					port
					(	acc_in,memory_in:in std_logic_vector(15 downto 0);
						cs:in std_logic_vector(31 downto 0);
						clk:in std_logic;
						mbr_out:out std_logic_vector(15 downto 0)
					);
				end mbr;
				
				architecture behave of mbr is
				begin
					process(clk)
						begin
							if clk'event and clk='1'then 
								if cs(15)='1'then 
									mbr_out								elsif cs(16)='1'then
									mbr_out								end if;
							end if;
					end process;
				end behave;