Analysis & Synthesis report for div
Sat Aug 25 16:02:47 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Messages
9. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Aug 25 16:02:47 2007 ;
; Quartus II Version ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name ; div ;
; Top-level Entity Name ; div ;
; Family ; MAX II ;
; Total logic elements ; 94 ;
; Total pins ; 3 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device ; EPM1270T144C5 ; ;
; Top-level entity name ; div ; div ;
; Family name ; MAX II ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ;
; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; div.v ; yes ; User Verilog HDL File ; E:/VERIL/shumaguan/div.v ;
+----------------------------------+-----------------+------------------------+------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 94 ;
; -- Combinational with no register ; 52 ;
; -- Register only ; 20 ;
; -- Combinational with a register ; 22 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 20 ;
; -- 3 input functions ; 0 ;
; -- 2 input functions ; 52 ;
; -- 1 input functions ; 2 ;
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 56 ;
; -- arithmetic mode ; 38 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 42 ;
; Total logic cells in carry chains ; 40 ;
; I/O pins ; 3 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 42 ;
; Total fan-out ; 250 ;
; Average fan-out ; 2.58 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |div ; 94 (94) ; 42 ; 0 ; 3 ; 0 ; 52 (52) ; 20 (20) ; 22 (22) ; 40 (40) ; 0 (0) ; |div ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 42 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sat Aug 25 16:02:46 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off div -c div
Info: Found 1 design units, including 1 entities, in source file div.v
Info: Found entity 1: div
Info: Elaborating entity "div" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at div.v(19): truncated value with size 32 to match size of target (25)
Warning (10230): Verilog HDL assignment warning at div.v(32): truncated value with size 32 to match size of target (15)
Info: Implemented 97 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 2 output pins
Info: Implemented 94 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Sat Aug 25 16:02:47 2007
Info: Elapsed time: 00:00:02
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/VERIL/shumaguan/div.map.smsg.
