使用max_plus2在FPGA下实现拔河游戏机的功能

				library ieee;
				use ieee.std_logic_1164.all;
				use ieee.std_logic_unsigned.all;
				
				entity hexin is
				 port(bego,over,left,right,cp,clear:in std_logic;
				                          
				                                  q:out std_logic_vector (14 downto 0));
				end hexin;
				
				architecture one of hexin is
				component zonghejishu
				port(bego,left,right,over,clear,cp:in std_logic;
				                 a,b,c,d:out std_logic);
				end component;
				
				component yima
				port(a,b,c,d:in std_logic;
				           y:out std_logic_vector(14 downto 0));
				end component;
				
				signal ya,yb,yc,yd:std_logic;
				begin
				u1:zonghejishu port map(bego,left,right,over,clear,cp,ya,yb,yc,yd);
				g1:yima        port map(ya,yb,yc,yd,q);
				end one;