Protel Design System Design Rule Check
PCB File : \Program Files\Altium2004\Examples\U盘电路设计\U盘电路设计.PcbDoc
Date : 2008-9-22
Time : 17:46:08
Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.3mm) (InNet('VCC'))
Rule Violations :0
Processing Rule : Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C1(104.14mm,118.872mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C2(109.22mm,118.872mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C3(73.66mm,109.728mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C4(73.66mm,106.68mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C5(73.66mm,103.632mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C6(74.168mm,100.584mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C7(74.168mm,97.536mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C8(74.676mm,94.488mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C9(96.52mm,111.76mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C10(102.616mm,111.76mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C11(110.744mm,94.488mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C12(104.648mm,94.488mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C13(65.024mm,100.076mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C14(104.14mm,115.316mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C15(109.728mm,115.316mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C16(115.316mm,115.316mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C17(50.8mm,118.364mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C18(61.976mm,118.364mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component C19(38.1mm,113.792mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component DS1(69.088mm,118.364mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SIP Component P1(58.928mm,93.472mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SIP Component P2(111.252mm,102.108mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R1(65.024mm,110.236mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R2(65.024mm,107.696mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R3(65.024mm,105.156mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R4(65.024mm,102.616mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R5(65.024mm,96.52mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R6(74.676mm,113.792mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R7(69.596mm,113.792mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R8(79.756mm,113.792mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R9(84.328mm,113.792mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R10(75.692mm,118.364mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R11(89.916mm,113.792mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R12(64.516mm,113.792mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R13(114.808mm,118.872mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R14(56.388mm,118.364mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R15(38.1mm,109.22mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R16(38.1mm,105.664mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SMT Small Component R17(38.1mm,102.108mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SOIC Component U1(90.932mm,102.616mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between Component U2(98.552mm,115.824mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between SIP Component U3(93.98mm,118.872mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between LCC Component U4(52.324mm,107.188mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Violation between Small Component Y1(45.212mm,118.872mm) on Top Layer and
Room U盘电路设计 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (InComponentClass('U盘电路设计'))
Rule Violations :44
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Broken-Net Constraint ( (All) )
Violation Net VCC is broken into 3 sub-nets. Routed To 92.59%
Subnet : P1-1 R16-1 U4-1 C19-1 U4-27 U4-32 U4-4 R2-2 R1-2 U4-43
R7-2 R8-2 R10-2 U4-39 R9-2 C8-2 C9-1 C7-2 C6-2 U2-5 C12-1
C5-2 C11-2 C13-2 C4-2 C3-2
Subnet : U1-12
Subnet : U1-36
Rule Violations :1
Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.2mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (All)
Violation Pad Free-0(37.846mm,119.38mm) Multi-Layer Actual Hole Size = 3mm
Violation Pad Free-1(121.92mm,119.634mm) Multi-Layer Actual Hole Size = 3mm
Violation Pad Free-2(121.92mm,91.694mm) Multi-Layer Actual Hole Size = 3mm
Violation Pad Free-3(38.481mm,91.313mm) Multi-Layer Actual Hole Size = 3mm
Rule Violations :4
Violations Detected : 49
Time Elapsed : 00:00:01
