一个模拟ISA界面的简易小程式

源代码在线查看: cud.v.bak

软件大小: 534 K
上传用户: xujinliner
关键词: ISA 模拟 程式
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相关代码

				// WARNING: Do NOT edit the input and output ports in this file in a text
				// editor if you plan to continue editing the block that represents it in
				// the Block Editor! File corruption is VERY likely to occur.
				
				// Copyright (C) 1991-2009 Altera Corporation
				// Your use of Altera Corporation's design tools, logic functions 
				// and other software and tools, and its AMPP partner logic 
				// functions, and any output files from any of the foregoing 
				// (including device programming or simulation files), and any 
				// associated documentation or information are expressly subject 
				// to the terms and conditions of the Altera Program License 
				// Subscription Agreement, Altera MegaCore Function License 
				// Agreement, or other applicable license agreement, including, 
				// without limitation, that your use is for the sole purpose of 
				// programming logic devices manufactured by Altera and sold by 
				// Altera or its authorized distributors.  Please refer to the 
				// applicable agreement for further details.
				
				
				// Generated by Quartus II Version 9.0 (Build Build 132 02/25/2009)
				// Created on Thu Mar 19 21:45:05 2009
				
				//  Module Declaration
				module CUD
				(
					// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
					clk, BALE, SA, IOW, IOR, SBHE, PC, PD, PA, PB, IOCS16, SD
					// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
				);
				// Port Declaration
				
					// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
					input clk;
					input BALE;
					input [15:0]SA;
					input IOW;
					input IOR;
					input SBHE;
					input [15:0]PC;
					input [15:0]PD;
					
					output [15:0]PA;
					output [15:0]PB;
					output IOCS16;
					inout [15:0]SD;
					reg [15:0]SDout,PA,PB;
					reg IOCS16;
					reg OE,holdIOR,holdIOW;
					// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
					
					assign SD = (OE)? SDout:16'bz;
					always@(posedge clk)
					begin
					
						//control IOCS#16 =1
						//if IOR ==1 && IOW ==1
						begin
							if(IOCS16 ==0)
							begin
								//hold IOR or IOW
								if(IOR==0)
									holdIOR = 1;
								else if(IOW ==0)
									holdIOW = 1;
								
								//Read Over or Write Over
								if(IOR & holdIOR || IOW & holdIOW)
									begin
									IOCS16 =1;
									holdIOR =0;
									holdIOW =0;
									end
							end
								
						end
						//check SA control IOCS#16
						//SA = 0x0300 OR 0x03100 IOCS#16 = 0 
						begin
							if (SA == 16'h0300)
								IOCS16 = 0;
							else if(SA == 16'h0310)
								IOCS16 = 0;
						end
						//IOR = 0 when OE = 1 begin READ
						begin
							if(IOR == 0)
								OE = 1;
							else if(IOR == 1)
								OE = 0;
						end
						
						//I/O read
						//IOR# = 0 0 AND SA = 0x0300 OR 0x0310
						//else SDout =0x0000
						begin
						if(IOR ==0 && SA == 16'h0300)
							SDout = PC;
						else if(IOR == 0 && SA == 16'h0310)
							SDout = PD;
						end
						
						//I/O write
						//IOW# = 0 AND SA = 0x0300 OR 0x0310
						begin
							if(IOW == 0 && SA == 16'h0300)
								PA 							else if(IOW == 0 && SA == 16'h0310)
								PB 						end
						
					end
					
				
				endmodule
				
				
							

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