`timescale 1 ps / 1 ps module DMA ( ///khoi port cua slave control cs, ck, reset, wr, rd, avalon_add, data_out, avalon_data, ///khoi port cua MasterRead MasterRead_read_data, read_wait_request, MasterRead_add, MasterRead_read, ///khoi port cua MasterWrite write_wait_request, MasterWrite_add, MasterWrite_write_data, MasterWrite_write); input ck, reset, cs, wr, rd, read_wait_request, write_wait_request; input [3:0] avalon_add; input [31:0] MasterRead_read_data; input [31:0] avalon_data; output [31:0] MasterWrite_write_data; output [31:0] MasterRead_add, data_out, MasterWrite_add; output MasterRead_read, MasterWrite_write; wire [31:0] avalon_write_add, avalon_read_add, FFT_data, MasterRead_data_out, number_of_bytes, fifo_2_data_in, fifo_2_write_data; wire read_start, fifo_1_write, fifo_1_full, fifo_1_empty, fifo_1_read, FFT_Read_finish, fifo_2_full, fifo_2_write, fifo_2_read, fifo_2_empty, core_finish; slave_control control ( //input .ck(ck), .reset(reset), .cs(cs), .wr(wr), .rd(rd), .add(avalon_add), .data_in(avalon_data), .finish(MasterWrite_finish), //output .data_out(data_out), .write_add(avalon_write_add), .read_add(avalon_read_add), .number_of_bytes(number_of_bytes), .start(read_start)); MasterRead read ( //input .ck(ck), .reset(reset), .start(read_start), .read_add(avalon_read_add), .MasterRead_read_data(MasterRead_read_data), .read_wait_request(read_wait_request), .number_of_bytes(number_of_bytes), .fifo_full(fifo_1_full), //output .MasterRead_add(MasterRead_add), .MasterRead_data_out(MasterRead_data_out), .MasterRead_read(MasterRead_read), .fifo_write(fifo_1_write), .finish()); FIFO2 fifo_1 ( .clock(ck), .data(MasterRead_data_out), .rdreq(fifo_1_read), .wrreq(fifo_1_write), .empty(fifo_1_empty), .full(fifo_1_full), .q(FFT_data)); FIFO2 fifo_2 ( .clock(ck), .data(fifo_2_data_in), .rdreq(fifo_2_read), .wrreq(fifo_2_write), .empty(fifo_2_empty), .full(fifo_2_full), .q(fifo_2_write_data)); MasterWrite write ( //input .ck(ck), .reset(reset), .start(core_finish), .write_add(avalon_write_add), .MasterWrite_data_in(fifo_2_write_data), .write_wait_request(write_wait_request), .number_of_bytes(number_of_bytes), .fifo_empty(fifo_2_empty), //output .MasterWrite_add(MasterWrite_add), .MasterWrite_write_data(MasterWrite_write_data), .MasterWrite_write(MasterWrite_write), .finish(MasterWrite_finish), .fifo_read(fifo_2_read)); endmodule ///////////////////////////////////////////////// module slave_control( //input ck, reset, cs, wr, rd, add, data_in, finish, //output data_out, write_add, read_add, number_of_bytes, start); input ck, reset, cs, wr, rd, finish; input [3:0] add; input [31:0] data_in; output [31:0] data_out; output reg start; output reg [31:0] write_add, read_add, number_of_bytes; reg data_out_reg; assign data_out = {31'd0,data_out_reg}; always @(posedge reset or posedge ck) if(reset) begin start write_add read_add number_of_bytes data_out_reg end else if((add==4'd0) & wr & cs) read_add else if((add==4'd1) & wr & cs) write_add else if((add==4'd2) & wr & cs) number_of_bytes else if((add==4'd3) & wr & cs) start else if((add==4'd4) & rd & cs) data_out_reg endmodule //////////////////////////////////////////////// module MasterRead( //input ck, reset, start, read_add, MasterRead_read_data, read_wait_request, number_of_bytes, fifo_full, //output MasterRead_add, MasterRead_data_out, MasterRead_read, fifo_write, finish ); input ck, reset, start, read_wait_request, fifo_full; input [31:0] read_add; input [31:0] MasterRead_read_data; input [31:0] number_of_bytes; output reg MasterRead_read, fifo_write, finish; output reg [31:0] MasterRead_add; output reg [31:0] MasterRead_data_out; reg tem_read; reg [31:0] count; reg [31:0] offset; //code always @(posedge reset or posedge ck) if(reset) begin MasterRead_read finish MasterRead_add fifo_write count offset tem_read end else if(start) begin MasterRead_add (read_add + {offset[31:5],offset[2],offset[3],offset[4],offset[1:0]}); offset offset + 32'd4; tem_read 1'b0; MasterRead_read tem_read; fifo_write = 32'd4)) ? 1'b1 : 1'b0; count count + 32'd4; finish 1'b1; MasterRead_data_out tem_read ? MasterRead_read_data : 32'dz; end endmodule module FIFO2 ( clock, data, rdreq, wrreq, empty, full, q); input clock; input [31:0] data; input rdreq; input wrreq; output empty; output full; output [31:0] q; wire sub_wire0; wire [31:0] sub_wire1; wire sub_wire2; wire empty = sub_wire0; wire [31:0] q = sub_wire1[31:0]; wire full = sub_wire2; scfifo scfifo_component ( .rdreq (rdreq), .clock (clock), .wrreq (wrreq), .data (data), .empty (sub_wire0), .q (sub_wire1), .full (sub_wire2) // synopsys translate_off , .aclr (), .almost_empty (), .almost_full (), .sclr (), .usedw () // synopsys translate_on ); defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.intended_device_family = "Stratix II", scfifo_component.lpm_numwords = 16, scfifo_component.lpm_showahead = "OFF", scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = 32, scfifo_component.lpm_widthu = 4, scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON", scfifo_component.use_eab = "ON"; endmodule module MasterWrite( //input ck, reset, start, write_add, MasterWrite_data_in, write_wait_request, number_of_bytes, fifo_empty, //output MasterWrite_add, MasterWrite_write_data, MasterWrite_write, finish, fifo_read); input ck, reset, start, write_wait_request, fifo_empty; input [31:0] write_add, number_of_bytes; input [31:0] MasterWrite_data_in; output reg MasterWrite_write, finish; output fifo_read; output [31:0] MasterWrite_add; output [31:0] MasterWrite_write_data; reg [31:0] offset; reg [31:0] count; //reg [1:0] a; //code assign fifo_read = (reset || (~start)) ? 1'b0 : ~write_wait_request & (~fifo_empty); assign MasterWrite_add = (write_wait_request || (~MasterWrite_write)) ? MasterWrite_add : write_add + offset-32'd4; assign MasterWrite_write_data = MasterWrite_data_in; always @(posedge reset or posedge ck) if(reset) begin MasterWrite_write finish //MasterWrite_add //fifo_read offset count //MasterWrite_write_data //a end else if(start) begin MasterWrite_write //MasterWrite_write_data //a finish count offset end endmodule
