使用VHDL开发的简易数字时钟软件

源代码在线查看: control.vhd

软件大小: 1341 K
上传用户: multicolor
关键词: VHDL 数字时钟 软件
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相关代码

				LIBRARY IEEE;
				USE IEEE.STD_LOGIC_1164.ALL;
				USE IEEE.STD_LOGIC_UNSIGNED.ALL;
				USE IEEE.STD_LOGIC_ARITH.ALL;
				ENTITY control IS
				 PORT( reset:  IN  STD_LOGIC;        --system reset signal
				       begend: IN  STD_LOGIC;        --key of begin&end
				       keyup:  IN  STD_LOGIC;        --set time value
				       enter:  IN  STD_LOGIC;        --enable the configuration of next time bit
				       settime:  OUT STD_LOGIC;      --output to inform module "clock" to adjust time according to the newly-set time
				       hourhset: OUT INTEGER RANGE 0 TO 2;        --HOUR high SET BY CONTROL PART
				       hourlset: OUT INTEGER RANGE 0 TO 9;        --HOUR low SET BY CONTROL PART
				       minhset:  OUT INTEGER RANGE 0 TO 5;        --MINUTE high SET BY CONTROL PART
				       minlset:  OUT INTEGER RANGE 0 TO 9;        --MINUTE low SET BY CONTROL PART
				       sechset:  OUT INTEGER RANGE 0 TO 5;        --SECOND high SET BY CONTROL PART
				       seclset:  OUT INTEGER RANGE 0 TO 9;        --SECOND low SET BY CONTROL PART
				       weekset:  OUT INTEGER RANGE 0 TO 7);
				END control;
				ARCHITECTURE archi OF control IS
				 TYPE STATE IS(sethh,sethl,setmh,setml,setsh,setsl,weekday,ini);  --seven operation states in the control part
				 SIGNAL adjsta:  STATE;
				 SIGNAL setmark: STD_LOGIC;
				 SIGNAL seclow,minlow,hourlow: INTEGER RANGE 0 TO 9;
				 SIGNAL sechigh,minhigh: INTEGER RANGE 0 TO 5;
				 SIGNAL hourhigh: INTEGER RANGE 0 TO 2;
				 SIGNAL week: INTEGER RANGE 0 TO 7;
				BEGIN
				 seclset				 sechset				 minlset				 minhset				 hourlset				 hourhset				 settime				 weekset				mark:  --this process will decide the output control signal "settime" for "clock" module
				PROCESS(begend)
				 begin
				  if reset='1' then
				     setmark				  elsif begend'event and begend='1' then
				     if setmark='1' then
				        setmark				     else
				        setmark				     end if;
				  end if;
				END PROCESS;
				normal_run:  --this process acts as core state machine
				 PROCESS(enter,reset)
				 BEGIN
				    IF reset='1' THEN
				       adjsta				    ELSIF enter='1' AND enter'event THEN
				          case adjsta IS
				               WHEN ini=>
				                    adjsta				               WHEN weekday=>
				                    adjsta				               WHEN sethh=>
				                    adjsta				               WHEN sethl=>
				                    adjsta				               WHEN setmh=>
				                    adjsta				               WHEN setml=>
				                    adjsta				               WHEN setsh=>
				                    adjsta				               WHEN setsl=>
				                    adjsta				
				           end case;
				   END IF;
				 END PROCESS;
				time_adjust:    --the set value increased as the "keyup" is pushed down
				  PROCESS(keyup)
				   BEGIN
				     if reset='1' then
				        hourhigh				        hourlow				        minhigh				        minlow				        sechigh				        seclow				        week				     elsif keyup='1' AND keyup'event THEN
				           case adjsta IS
				                WHEN sethh=>
				                     hourhigh				                WHEN sethl=>
				                     hourlow				                WHEN setmh=>
				                     minhigh				                WHEN setml=>
				                     minlow				                WHEN setsh=>
				                     sechigh				                WHEN setsl=>
				                     seclow				                WHEN weekday=>
				                     week				                WHEN ini=>
				                     NULL;
				          end case;
				     end if;
				  END PROCESS;
				END archi;
				
							

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